FPGA-based enhanced probabilistic convergent weightless network for human iris recognition

This paper investigates how human identification and identity verification can be performed by the application of an FPGA based weightless neural network, entitled the Enhanced Probabilistic Convergent Neural Network (EPCN), to the iris biometric modality. The human iris is processed for feature vectors which will be employed for formation of connectivity, during learning and subsequent recognition. The pre-processing of the iris, prior to EPCN training, is very minimal. Structural modifications were also made to the Random Access Memory (RAM) based neural network which enhances its robustness when applied in real-time

Maths vs (meta)modelling: Are we reinventing the wheel?

In the past, specification of languages and data structures has traditionally been formally achieved using mathematical notations. This is very precise and unambiguous, however it does not map easily to modern programming languages and many engineers are put off by mathematical notation. Recent developments in graphical specification of structures, drawing from Object-Oriented programming languages, has lead to the development of Class Diagrams as a well-used means to define data structures. We show in this paper that there are strong parallels between the two techniques, but that also there are some surprising differences

A Fingerprint Identification System Using Adaptive FPGA-Based Enhanced Probabilistic Convergent Network

This paper explores the biomeric identification and verification of human subjects via fingerprints utilising an adaptive FPGA-based weightless neural networks. The exploration espoused here is a hardware-based system motivated by the need for accurate and rapid response to identification of fingerprints which may be lacking in other alternative systems such as software based neural networks. The fingerprints are pre-processed and binarised, and the binarized fingerprints are partitioned into train- and test-set for the FPGA-based neural network. The neural network emloyed in this exploration is known as Ehnanced Convergent Network (EPCN). The results obtained are compared to other alternative systems. They demonstrate the suitability of the FPGA-based EPCN for such tasks. © 2009 IEEE

An advanced combination strategy for multi-classifiers employed in large multi-class problem domains

Traditional artificial neural architectures possess limited ability to address the scale problem exhibited by a large number of distinct pattern classes and limited training data. To address these problems, this paper explores a novel advanced encoding scheme, which reduces both memory demand and execution time, and provides improved performance. The novel advanced encoding scheme known as the engine encoding, have been implemented in a multi-classifier, which combines the scaled probabilities, configuration information, and the discriminating abilities of the associated component classifiers. The problems of overloading and saturation experienced by traditional networks are solved by training the base classifiers on differing sub-sets of the required pattern classes and allowing the combiner classifier to derive a solution. Current Multi-classifier Systems are easily biased when trained on one class more often than another class, when patterns representing a class are very large compared to the rest, or when the multi-classifier depends on a certain fixed order of arrangement of pattern classes. A unique statistical arrangement method is hereby presented which aims to solve the bias problem. This statistical arrangement method also enhances independence of component classifiers. The system is demonstrated on the exemplar of fingerprint identification and utilizes a Weightless Neural System called the Enhanced Probabilistic Convergent Neural Network (EPCN) in a Multi-classifier System. © 2010 Elsevier B.V. All rights reserved

A Framework for Self-Diagnosis and Condition Monitoring for Embedded Systems Using a SOM-Based Classifier

This paper presents a system level framework for System-on-Chip (SoC) based embedded devices that may include adaptive and reconfigurable elements. Current development support and debugging solutions are highly dependant on off-line post-mortem style inspection, and even those that utilise tracing for real-time and schedule-critical systems rely on external development tools and environments. This new framework introduces an AI-lead infrastructure that has the potential to reduce much of the development effort while complementing existing debugging circuits. Specifically this paper investigates how to use a Kohonen self-organising map (SOM) as a classifier, and shows a preliminary investigation into how to determine the quality of a map after training. This classifier is a first step in diagnosing failure, degradation and anomalies (i.e. provides condition monitoring) in an embedded system from a system level point of view, and in the larger task of self-diagnosis of an embedded system. © 2008 IEEE

A Model-Driven Development Approach to Mapping UML State Diagrams to Synthesizable VHDL

With the continuing rise in the complexity of embedded systems, there is an emerging need for a higher level modelling environment that facilitates efficient handling of this complexity. The aim here is to produce such a high level environment using Model Driven Development (MDD) techniques that maps a high level abstract description of an electronic embedded system into its low level implementation details. The Unified Modelling Language (UML) is a high level graphical based language that is broad enough in scope to model embedded systems hardware circuits. The authors have developed a framework for deriving Very High Speed Integrated Circuits Hardware Description Language (VHDL) code from UML state diagrams and defined a set of rules that enable automated generation of synthesisable VHDL code from UML specifications using MDD techniques. By adopting the techniques and tools described in this paper the design and implementation of complex state-based systems is greatly simplified. © 2008 IEEE

SiTra: Simple Transformations in Java

A number of different Model Transformation Frameworks (MTF) are being developed, each of them requiring a user to learn a different language and each possessing its own specific language peculiarities, even if they are based on the QVT standard. To write even a simple transformation, these MTFs require a large amount of learning time. We describe in this paper a minimal, Java based, library that can be used to support the implementation of many practical transformations. Use of this library enables simple transformations to be implemented simply, whilst still providing some support for more complex transformations